US 12,294,376 B2
Differential clock duty cycle corrector circuits
Santosh Mahadeo Narawade, Bangalore (IN); Jithin K, Bangalore (IN); and Ayan Dutta, Barasat (IN)
Assigned to Alphawave Semi, Inc., Milpitas, CA (US)
Filed by Open Silicon, Inc., Milpitas, CA (US)
Filed on Dec. 29, 2022, as Appl. No. 18/091,114.
Claims priority of provisional application 63/295,816, filed on Dec. 31, 2021.
Prior Publication US 2023/0216489 A1, Jul. 6, 2023
Int. Cl. H03K 5/156 (2006.01); H03K 3/017 (2006.01); H03K 5/135 (2006.01)
CPC H03K 5/1565 (2013.01) [H03K 3/017 (2013.01); H03K 5/135 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a differential clock duty cycle adjuster circuitry connected between a first input node, a second input node, a first output node, and a second output node, the differential clock duty cycle adjuster circuitry comprising:
a first PMOS transistor with a gate terminal connected to the first input node, a source terminal connected to a first current source, and a drain terminal connected to the second output node;
a second PMOS transistor with a gate terminal connected to the second input node, a source terminal connected to the first current source, and a drain terminal connected to the first output node;
a first NMOS transistor with a gate terminal connected to the first input node, a drain terminal connected to the first current source, and a source terminal connected to the first output node; and
a second NMOS transistor with a gate terminal connected to the second input node, a drain terminal connected to the first current source, and a source terminal connected to the second output node.