US 12,294,372 B2
Low power crystal oscillator with automatic amplitude control
Nitin Jain, Greater Noida (IN); Anand Kumar, Noida (IN); and Kallol Chatterjee, Kolkata (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 25, 2023, as Appl. No. 18/323,998.
Claims priority of provisional application 63/350,101, filed on Jun. 8, 2022.
Prior Publication US 2023/0412155 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/03 (2006.01); H03K 3/012 (2006.01); H03K 3/354 (2006.01)
CPC H03K 3/0307 (2013.01) [H03K 3/012 (2013.01); H03K 3/3545 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A low power crystal oscillator circuit, comprising:
a crystal;
a high power supply;
a low power supply;
a first capacitor having a first terminal coupled to the crystal;
a second capacitor having a first terminal coupled to the crystal;
a first current mirror transistor having a first terminal coupled to the high power supply, and a second terminal coupled to a gate terminal, the first current mirror transistor having a channel with a first width to length ratio;
a first current source configured to output a current of a first value, the first current source having a first terminal coupled to the second terminal of the first current mirror transistor;
a second current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminal of the first current mirror transistor, a second terminal coupled to the crystal, and the second current mirror transistor having a second width to length ratio that is X times greater than the first width to length ratio;
a third current mirror transistor having a first terminal coupled to the high power supply and a second terminal coupled to a gate terminal of the third current mirror transistor, the third current mirror transistor having a third width to length ratio;
a second current source configured to output a current of a second value, the second current source having a first terminal coupled to the second terminal of the third current mirror transistor;
a fourth current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminal of the third current mirror transistor, and a second terminal coupled to the second terminal of the second current mirror transistor, the fourth current mirror transistor having a fourth width to length ratio that is Y times greater than the third width to length ratio; and
a fifth current mirror transistor having a first terminal coupled to the high power supply, a gate terminal coupled to the gate terminals of the third current mirror transistor and the fourth current mirror transistor, and a second terminal coupled to the second terminal of the first current mirror transistor, the fifth current mirror transistor having a fifth width to length ratio that is Z times smaller than the third width to length ratio, the gate terminals of the third current mirror transistor, the fourth current mirror transistor, and the fifth current mirror transistor are coupled to the crystal.