US 12,294,370 B1
Area optimized ferroelectric or paraelectric based low power multiplier
Amrita Mathuriya, Portland, OR (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); Rafael Rios, Austin, TX (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Sep. 3, 2021, as Appl. No. 17/467,100.
Application 17/467,100 is a continuation of application No. 17/465,784, filed on Sep. 2, 2021.
Int. Cl. H03K 19/23 (2006.01); H01L 49/02 (2006.01)
CPC H03K 19/23 (2013.01) [H01L 28/55 (2013.01); H01L 28/65 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an AND gate comprising a majority gate or a minority gate having non-linear polar material;
a buffer coupled to an output of the AND gate; and
a 1-bit full adder comprising a majority gate or a minority gate coupled to the buffer, wherein the 1-bit full adder comprises non-linear polar material.