US 12,294,369 B2
Asymmetrical clock separation and stage delay optimization in single flux quantum logic
Takeo Yasuda, Nara (JP); Robert K. Montoye, Yorktown Heights, NY (US); and Gerald W. Gibson, Danbury, CT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 26, 2022, as Appl. No. 17/729,614.
Prior Publication US 2023/0344432 A1, Oct. 26, 2023
Int. Cl. H03K 19/195 (2006.01); G06F 1/06 (2006.01); H03K 5/00 (2006.01); H03K 5/01 (2006.01)
CPC H03K 19/195 (2013.01) [G06F 1/06 (2013.01); H03K 5/01 (2013.01); H03K 2005/00078 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor configured to:
implement a pipeline;
receive at least one pair of SFQ clock signals, wherein each pair of SFQ clock signals includes:
a first SFQ clock signal;
a second SFQ clock signal that is out of phase with the first SFQ clock signal, wherein the second SFQ clock signal has same frequency as the first SFQ clock signal;
for each pair of SFQ clock signals:
define a first clock cycle based on a delay from the first SFQ clock signal to the second SFQ clock signal;
define a second clock cycle based on a delay from the second SFQ clock signal to the first SFQ clock signal of a next pair of SFQ clock signals, wherein the second clock cycle is greater than the first clock cycle; and
assign the first clock cycle and the second clock cycle to different stages of the pipeline, wherein the assignment is based on delays of the different stages.