US 12,294,368 B2
Three-dimensional stacked programmable logic fabric and processor design architecture
Rahul Pal, Bangalore (IN); Dheeraj Subbareddy, Portland, OR (US); Mahesh Kumashikar, Bangalore (IN); Dheemanth Nagaraj, Bangalore (IN); Rajesh Vivekanandham, Bangalore (IN); Anshuman Thakur, Beaverton, OR (US); Ankireddy Nalamalpu, Portland, OR (US); Md Altaf Hossain, Portland, OR (US); and Atul Maheshwari, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,119.
Prior Publication US 2022/0014202 A1, Jan. 13, 2022
Int. Cl. H03K 19/177 (2020.01); G06F 15/78 (2006.01); G06F 30/34 (2020.01); H03K 19/17758 (2020.01); H03K 19/17796 (2020.01); H03K 19/08 (2006.01)
CPC H03K 19/17796 (2013.01) [G06F 15/7892 (2013.01); G06F 30/34 (2020.01); H03K 19/17758 (2020.01); H03K 19/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor having one or more cores; and
a programmable fabric device, wherein the processor is stacked in a three-dimensional orientation above the programmable fabric device, and wherein the programmable fabric device comprises:
a programmable fabric comprising a plurality of partitions configured to perform fine-grained acceleration operations; and
one or more interfaces configured to provide connections between the
programmable fabric and the processor, wherein the programmable fabric device is operable to:
receive one or more sets of data from a processor pipeline via the one or more interfaces;
configure a first portion of the programmable fabric comprising the plurality of partitions coupled to one or more executions units of the one or more cores of the processor to perform the fine-grained acceleration operations, wherein the fine-grained acceleration operations comprise extending an instruction-set architecture of the processor to initiate a custom opcode space to interface with the programmable fabric;
receive one or more additional sets of data from the processor pipeline; and
configure a second portion of the programmable fabric comprising one or more system memory portions reserved for the programmable fabric to interface with the processor to perform coarse-grained acceleration operations.