US 12,294,367 B2
Level shifter with voltage stress durability and method for driving the same
Chun-Yuan Lo, Hsinchu County (TW); Wu-Chang Chang, Hsinchu County (TW); and Bo-Chang Li, Hsinchu County (TW)
Assigned to eMemory Technology Inc., Hsinchu (TW)
Filed by eMemory Technology Inc., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,682.
Claims priority of provisional application 63/397,394, filed on Aug. 12, 2022.
Prior Publication US 2024/0056080 A1, Feb. 15, 2024
Int. Cl. H03K 19/01 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/018528 (2013.01) [G11C 16/102 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A level shifter, comprising:
a first cross-coupled transistor pair, coupled with a first power terminal;
a first biased transistor pair, coupled in series with the first cross-coupled transistor pair, and controlled by a first reference voltage;
a second biased transistor pair, coupled in series with the first biased transistor pair, and controlled by a pair of first differential control voltages;
a third biased transistor pair, coupled in series with the second biased transistor pair, and controlled by a second reference voltage lower than the first reference voltage;
a first differential input pair, coupled in series with the third biased transistor pair, and controlled by a pair of differential input voltages; and
a first sub level shifter, configured to generate the pair of first differential control voltages according to the pair of differential input voltages, the first reference voltage and the second reference voltage, wherein the pair of first differential control voltages is switched between the first reference voltage and the second reference voltage;
wherein the level shifter is configured to output a pair of differential output voltages through an inverted output terminal and a non-inverted output terminal coupled with the second biased transistor pair,
wherein the pair of differential output voltages comprises a non-inverted output voltage and an inverted output voltage,
wherein the pair of differential input voltages comprises a non-inverted input voltage and an inverted input voltage that are converted to the non-inverted output voltage and the inverted output voltage, respectively,
wherein the pair of first differential control voltages comprises a first control voltage and a second control voltage configured to control magnitude of the inverted output voltage and magnitude of the non-inverted output voltage, respectively, and
wherein when the non-inverted input voltage is higher than the inverted input voltage, the first control voltage is lower than the second control voltage.