US 12,294,364 B2
Transistor with integrated turn-off slew rate control
Santosh Sharma, Austin, TX (US); and Mei Yu Soh, Singapore (SG)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Aug. 25, 2023, as Appl. No. 18/455,669.
Prior Publication US 2025/0070781 A1, Feb. 27, 2025
Int. Cl. H03K 19/003 (2006.01); H03K 17/0412 (2006.01); H03K 17/06 (2006.01)
CPC H03K 19/00384 (2013.01) [H03K 17/04123 (2013.01); H03K 2017/066 (2013.01); H03K 2217/0036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a transistor having a source region and a drain region, wherein the transistor is an enhancement mode transistor; and
a slew rate controller connected to the source region and to the drain region, wherein the slew rate controller increases drain-source capacitance of the transistor to slow a slew rate, when a drain voltage at the drain region rises at least to a predetermined positive drain voltage level and the slew rate is positive.