US 12,294,363 B2
Circuit for mitigating single-event-transients
Joseph Sylvester Chang, Singapore (SG); Wei Shu, Singapore (SG); Yong Qu, Singapore (SG); Kwen Siong Chong, Singapore (SG); and Arunjai Mittal, Singapore (SG)
Assigned to ZERO-ERROR SYSTEMS PTE. LTD, Singapore (SG)
Appl. No. 17/767,016
Filed by ZERO-ERROR SYSTEMS PTE. LTD, Singapore (SG)
PCT Filed Oct. 7, 2020, PCT No. PCT/SG2020/050568
§ 371(c)(1), (2) Date Apr. 6, 2022,
PCT Pub. No. WO2021/071426, PCT Pub. Date Apr. 15, 2021.
Claims priority of application No. 10201909392R (SG), filed on Oct. 8, 2019.
Prior Publication US 2022/0368327 A1, Nov. 17, 2022
Int. Cl. G11C 7/10 (2006.01); H03K 3/037 (2006.01); H03K 17/687 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/00338 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); H03K 3/0375 (2013.01); H03K 17/6872 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit for mitigating single-effect-transients (SETs) having a first input, a second input, a first complementary input, a second complementary input, a first output and a second output, and comprising:
a first sub-circuit comprising:
a first p-type transistor arrangement comprising at least one p-type transistor configured to generate the first output, and
a first n-type transistor arrangement comprising at least one n-type transistor configured to generate the second output; and
a second sub-circuit comprising:
a connecting p-type transistor arrangement comprising at least one p-type transistor,
a connecting n-type transistor arrangement comprising at least one n-type transistor connected in series to the connecting p-type transistor arrangement, wherein a drain terminal of the at least one p-type transistor in the connecting p-type transistor arrangement and a drain terminal of the at least one n-type transistor in the connecting n-type transistor arrangement are electrically coupled to each other, and
a second p-type transistor arrangement comprising at least one p-type transistor and a second n-type transistor arrangement comprising at least one n-type transistor, wherein
the first output is further electrically coupled to a drain terminal of the at least one p-type transistor in the second p-type transistor arrangement,
the second output is further electrically coupled to a drain terminal of the at least one n-type transistor in the second n-type transistor arrangement,
a gate terminal of the at least one p-type transistor in the connecting p-type transistor arrangement and a gate terminal of the at least one n-type transistor in the second n-type transistor arrangement are controlled by the first complementary input,
a gate terminal of the at least one n-type transistor in the connecting n-type transistor arrangement and a gate terminal of the at least one p-type transistor in the second p-type transistor arrangement are controlled by the second complementary input,
a source terminal of the at least one p-type transistor in the second p-type transistor arrangement is electrically coupled to VDD, and
a source terminal of the at least one n-type transistor in the second n-type transistor arrangement is electrically coupled to VSS,
wherein the first output and the second output are electrically coupled to each other through the second sub-circuit through the connecting p-type transistor arrangement of the second sub-circuit and the connecting n-type transistor arrangement of the second sub-circuit.