US 12,294,361 B2
Output stage of ethernet transmitter
Chien-Hui Tsai, Hsinchu (TW); Hung-Chen Chu, Hsinchu (TW); and Yung-Tai Chen, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Dec. 5, 2022, as Appl. No. 18/074,825.
Claims priority of application No. 111100140 (TW), filed on Jan. 3, 2022.
Prior Publication US 2023/0216493 A1, Jul. 6, 2023
Int. Cl. H03K 17/693 (2006.01); H03H 11/28 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/693 (2013.01) [H03H 11/28 (2013.01); H03K 17/6872 (2013.01); H03K 17/6874 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An output stage of an Ethernet transmitter, which is coupled to a resistor, comprising:
a first output terminal;
a second output terminal, wherein the resistor is coupled between the first output terminal and the second output terminal;
a first transistor having a first source, a first drain, and a first gate, wherein the first source is coupled to a first reference voltage, and the first drain is coupled to the second output terminal; and
a first transistor group coupled to the first reference voltage and the first output terminal;
wherein the first transistor group comprises a plurality of transistors that are connected in parallel, and a magnitude of a current flowing to the first output terminal is related to the number of transistors that are turned on;
wherein a first voltage at the first output terminal is substantially equal to a second voltage at the second output terminal so that there is no current on the resistor.