US 12,294,358 B2
Integrated electronic system with an improved power-on reset circuit and method for controlling the integrated electronic system
Riccardo Condorelli, Catania (IT); Antonino Mondello, Messina (IT); Michele Alessandro Carrano, Catania (IT); Daniele Mangano, San Gregorio di Catania (IT); Fabien Laplace, Charavines (FR); Luc Garcia, Saint Paul de Varces (FR); and Michel Cuenca, Septemes les Vallons (FR)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jan. 10, 2024, as Appl. No. 18/409,083.
Claims priority of application No. 102023000000216 (IT), filed on Jan. 11, 2023.
Prior Publication US 2024/0235546 A1, Jul. 11, 2024
Int. Cl. H03K 17/22 (2006.01); G11C 5/14 (2006.01)
CPC H03K 17/22 (2013.01) [G11C 5/14 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An integrated electronic system, comprising:
a digital stage of a resettable type that is configured for operation when a supply voltage is higher than a main voltage threshold, said digital stage comprising a non-volatile memory configured to store a digital code, and a reading stage coupled to the non-volatile memory;
a main power-on reset circuit configured to generate a main reset signal having a respective logic reset value that activates reset of the reading stage and a respective logic non-reset value that deactivates reset of the reading stage;
wherein the main power-on reset circuit is configured to:
when the main reset signal is equal to the respective logic reset value and the supply voltage overcomes a first operative threshold, set the main reset signal to the respective logic non-reset value; and
when the main reset signal is equal to the respective logic non-reset value and the supply voltage drops below a second operative threshold, set the main reset signal to the respective logic reset value;
a volatile memory of a resettable type that is coupled to the reading stage, wherein the volatile memory is configured to store a default value when subject to reset;
an auxiliary power-on reset circuit configured to generate an auxiliary reset signal having a respective logic reset value activating reset of the volatile memory and having a respective logic non-reset value deactivating reset of the volatile memory;
wherein the auxiliary power-on reset circuit being configured to:
when the auxiliary reset signal is equal to the respective logic reset value and the supply voltage overcomes a first auxiliary operative threshold, set the auxiliary reset signal to the respective logic non-reset value; and
when the auxiliary reset signal is equal to the respective logic non-reset value and the supply voltage drops below a second auxiliary operative threshold, set the auxiliary reset signal to the respective logic reset value;
wherein the first and the second auxiliary operative thresholds are lower than the main voltage threshold; and
wherein the reading stage is configured to load, following the deactivation of the reset of the reading stage, the digital code into the volatile memory for storage until the reset of the volatile memory is activated;
wherein the main power-on reset circuit is configured to function in a non-trimmed configuration when the volatile memory respectively stores the default value, where the first and the second operative thresholds respectively fall within a first non-trimmed voltage range and a second non-trimmed voltage range which extend above said main voltage threshold; and
wherein the main power-on reset circuit is configured to function in a trimmed configuration when the volatile memory respectively stores the digital code, where the first and the second operative thresholds respectively fall within a first trimmed voltage range and a second trimmed voltage range which respectively fall inside the first and second non-trimmed voltage ranges.