US 12,294,316 B2
Controller for a power converter and a method of controlling a power converter
Lukas Vaculik, Valasske Mezirici (CZ); Radek Holis, Karolinka (CZ); and Ivan Sieklik, Slovakia (SK)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Mar. 31, 2023, as Appl. No. 18/193,919.
Claims priority of application No. 22163791 (EP), filed on Mar. 23, 2022.
Prior Publication US 2024/0333177 A1, Oct. 3, 2024
Int. Cl. H02M 7/5387 (2007.01); H02M 1/00 (2006.01)
CPC H02M 7/53871 (2013.01) [H02M 1/0003 (2021.05)] 16 Claims
OG exemplary drawing
 
1. A controller for a power converter, the controller comprising:
a generator module configured to generate a sequence of pulses each having a width that is defined by a rise moment value stored in a rise moment register of the generator module and a fall moment value stored in a fall moment register of the generator module, the sequence of pulses having a repetition rate that is modulated by a repetition period value stored in a repetition period register of the generator module;
a memory having a table of rise moment values, a table of fall moment values, and a table of repetition period values that are configured to be written into the rise moment register, the fall moment register and the repetition period register, respectively;
a direct memory access (DMA) module coupled to the generator module and to the memory and configured to write the rise moment values of the table of rise moment values, the fall moment values of the table of fall moment values, and the repetition period values of the table of repetition period values into the rise moment register, the fall moment register and the repetition period register, respectively, in response to a DMA trigger;
a core coupled to the DMA module and configured to write the rise moment values, the fall moment values, and the repetition period values into the table of rise moment values, the table of fall moment values, and the table of repetition period values, respectively; and
an input signal interface coupled to the core and configured to receive an input signal, wherein the core is configured to modify the rise moment, fall moment, and repetition period values in response to the input signal and to write the modified rise moment, fall moment, and repetition period values into the memory.