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1. A circuit for balancing energy management over time comprising a computing center and at least three connection points (S.k) where energy is managed, k being a sequential number of the connection point, wherein each of these connection points (S.k) is equipped with a measuring device (A.k) for energy management data measurement over time, the measuring device (A.k) being data-connected to the computing center comprising at least one processor, wherein at least one of the connection points (S.k) includes an energy production source and wherein at least one of the connection points (S.k) comprises an energy consuming appliance, wherein all the connection points (S.k) are also power-connected to a distribution network, wherein the circuit comprises at least three logical control nodes (N.i.j) which are arranged in a logically interconnected tree structure in which they are divided into at least two levels, the levels being numbered by first sequential numbers i from 1 to m, m being the total number of levels, whereas in the frame of the same level with the same first sequential number i, the logical control nodes (N.i.j) are numbered by a second sequential number j, and the logically interconnected tree structure is arranged so that in the lowest first level, there is one central logical control node (N.1.1), from which the tree structure branches to higher levels, wherein the first sequential number indicating the level increases in the direction from of this central control node (N.1.1), and wherein each logical control node (N.m.j) of the highest m-th level is logically connected to at least one of the connection points (S.k), the logical connection structure comprising at least one branching with at least two branches between the logical control nodes (N.2.j) of the second level and the connection points (S.k), characterized in that each logical control node (N.i.j) is a part of the computing center and that there is at least one real processor among the computing center processors having at least two cores and which is divided into at least two virtual processors, each having at least one core, wherein the sum of the number of the real processors not divided into virtual ones and of the number of the virtual processors is equal to or greater than the total number of all logical control nodes (N.i.j) of all levels, each of these logical control nodes (N.i.j) being assigned one of these virtual or real processors, and the logical interconnection between the logical control nodes (N.i.j) is implemented as a logical interconnection between the individual processors assigned to these logical control nodes (N.i.j).
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