US 12,294,031 B2
Semiconductor device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 25, 2024, as Appl. No. 18/422,699.
Application 18/422,699 is a continuation of application No. 17/946,116, filed on Sep. 16, 2022, granted, now 11,916,150.
Application 17/946,116 is a continuation of application No. 17/408,572, filed on Aug. 23, 2021, granted, now 11,575,049, issued on Feb. 7, 2023.
Application 17/408,572 is a continuation of application No. 16/925,381, filed on Jul. 10, 2020, granted, now 11,127,858, issued on Sep. 21, 2021.
Application 16/925,381 is a continuation of application No. 16/416,394, filed on May 20, 2019, granted, now 10,714,630, issued on Jul. 14, 2020.
Application 16/416,394 is a continuation of application No. 16/244,193, filed on Jan. 10, 2019, granted, now 10,297,693, issued on May 21, 2019.
Application 16/244,193 is a continuation of application No. 16/022,806, filed on Jun. 29, 2018, granted, now 10,181,530, issued on Jan. 15, 2019.
Application 16/022,806 is a continuation of application No. 15/168,293, filed on May 31, 2016, granted, now 10,026,848, issued on Jul. 17, 2018.
Application 15/168,293 is a continuation of application No. 13/975,422, filed on Aug. 26, 2013, granted, now 9,362,412, issued on Jun. 7, 2016.
Application 13/975,422 is a continuation of application No. 12/731,722, filed on Mar. 25, 2010, granted, now 8,519,929, issued on Aug. 27, 2013.
Claims priority of application No. 2009-077955 (JP), filed on Mar. 27, 2009.
Prior Publication US 2024/0413249 A1, Dec. 12, 2024
Int. Cl. G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H01L 21/477 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7869 (2013.01) [G09G 3/20 (2013.01); G09G 3/3648 (2013.01); G11C 19/28 (2013.01); H01L 21/477 (2013.01); H01L 27/1255 (2013.01); H01L 27/127 (2013.01); G09G 2300/04 (2013.01); G09G 2310/0275 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to an output signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the output signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line,
wherein a gate of the third transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the first power supply line,
wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,
wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the first power supply line,
wherein a gate of the eighth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the seventh transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the first power supply line,
wherein a gate of the ninth transistor is electrically connected to a second signal line,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line, and
wherein a gate of the tenth transistor is electrically connected to the second signal line.