US 12,294,027 B2
Semiconductor device having doped epitaxial region and its methods of fabrication
Anand S. Murthy, Portland, OR (US); Daniel Boune Aubertine, North Plains, OR (US); Tahir Ghani, Portland, OR (US); and Abhijit Jayant Pethe, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 8, 2024, as Appl. No. 18/407,007.
Application 18/407,007 is a division of application No. 17/161,534, filed on Jan. 28, 2021, granted, now 11,908,934.
Application 14/059,398 is a division of application No. 12/643,912, filed on Dec. 21, 2009, granted, now 8,598,003, issued on Dec. 3, 2013.
Application 17/161,534 is a continuation of application No. 14/059,398, filed on Oct. 21, 2013, granted, now 10,957,796, issued on Mar. 23, 2021.
Prior Publication US 2024/0145592 A1, May 2, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7834 (2013.01) [H01L 21/02057 (2013.01); H01L 21/02381 (2013.01); H01L 21/0243 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/0262 (2013.01); H01L 21/02636 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 21/28079 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01); H01L 29/7853 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a silicon body continuous with and extending from a monocrystalline silicon substrate through an isolation region, the silicon body having a top and laterally opposite sidewalls;
a gate electrode over the top and laterally opposite sidewalls of the silicon body and over a portion of the isolation region, the gate electrode defining a channel region in the silicon body;
an epitaxial source material in a first recess in the silicon body laterally adjacent a first end of the channel region at a first side of the gate electrode, the epitaxial source material comprising a first atomic concentration of silicon;
a first semiconductor cap on the epitaxial source material, the first semiconductor cap comprising a second atomic concentration of silicon, the second atomic concentration of silicon greater than the first atomic concentration of silicon;
an epitaxial drain material in a second recess in the silicon body laterally adjacent a second end of the channel region at a second side of the gate electrode, the second side of the gate electrode opposite the first side of the gate electrode, the epitaxial drain material comprising the first atomic concentration of silicon;
a second semiconductor cap on the epitaxial drain material, the second semiconductor cap comprising the second atomic concentration of silicon;
a first dielectric spacer adjacent the first side of the gate electrode, wherein the first semiconductor cap is in contact with a bottom surface of the first dielectric spacer; and
a second dielectric spacer adjacent the second side of the gate electrode, wherein the second semiconductor cap is in contact with a bottom surface of the second dielectric spacer.