US 12,294,024 B2
Method of manufacturing semiconductor device
Hajime Watakabe, Tokyo (JP); Masashi Tsubuku, Tokyo (JP); Kentaro Miura, Tokyo (JP); Akihiro Hanada, Tokyo (JP); and Takaya Tamaru, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Apr. 26, 2022, as Appl. No. 17/660,729.
Claims priority of application No. 2021-080436 (JP), filed on May 11, 2021.
Prior Publication US 2022/0367691 A1, Nov. 17, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/426 (2006.01); H01L 21/4757 (2006.01); H01L 21/4763 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 21/426 (2013.01); H01L 21/47573 (2013.01); H01L 21/47635 (2013.01); H01L 29/401 (2013.01); H01L 29/78621 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base;
forming a patterned resist on the metal layer;
etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer;
reducing a volume of the resist to expose an upper surface along a side surface of the metal layer;
etching the metal layer using the resist as a mask, to form a gate electrode including a first side surface and to expose an upper surface along a second side surface of the buffer layer; and
carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.