US 12,294,023 B2
Method of manufacturing a semiconductor device having corner spacers adjacent a fin sidewall
Chen-Ping Chen, Toucheng Township (TW); Kuei-Yu Kao, Hsinchu (TW); Shih-Yao Lin, New Taipei (TW); Chih-Han Lin, Hsinchu (TW); Ming-Ching Chang, Hsinchu (TW); and Chao-Cheng Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/818,647.
Application 17/818,647 is a division of application No. 17/101,291, filed on Nov. 23, 2020, granted, now 11,769,821.
Claims priority of provisional application 63/025,332, filed on May 15, 2020.
Prior Publication US 2022/0384617 A1, Dec. 1, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/7851 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a fin protruding from a substrate;
forming a dummy gate structure extending over a channel region of the fin;
forming a first spacer layer on sidewalls of the dummy gate structure;
epitaxially growing source/drain regions on the fin adjacent the channel region;
removing the dummy gate structure to form a recess;
depositing a second spacer layer within the recess;
performing an etching process on the second spacer layer, wherein the etching process selectively etches the second spacer layer more than the first spacer layer, wherein after performing the etching process, remaining portions of the second spacer layer remain within the recess to form corner spacers, wherein the corner spacers are separated from each other, wherein the corner spacers are located at corner regions of the recess adjacent the fin; and
forming a replacement gate structure within the recess and on the corner spacers.
 
8. A method comprising:
forming a fin on a semiconductor substrate;
depositing a first dielectric layer on a top surface and a sidewall of the fin;
forming epitaxial source/drain regions in the fin adjacent the first dielectric layer;
depositing a second dielectric layer on a top surface and a sidewall of the first dielectric layer;
depositing a third dielectric layer on a sidewall of the second dielectric layer and on a sidewall of the first dielectric layer;
etching the second dielectric layer to expose first surfaces of the first dielectric layer and the third dielectric layer;
depositing a fourth dielectric layer on the exposed first surfaces of the first dielectric layer and the third dielectric layer;
etching the fourth dielectric layer to expose second surfaces of the first dielectric layer and the third dielectric layer, wherein portions of the fourth dielectric layer remain on the first surfaces of the first dielectric layer and the third dielectric layer; and
forming a gate structure on a surface of the fourth dielectric layer and on the second surfaces of the first dielectric layer and the third dielectric layer.
 
15. A method comprising:
forming a fin extending on a substrate in a first direction;
forming a dummy dielectric layer over the fin;
forming a gate spacer on the dummy dielectric layer and extending over the fin in a second direction perpendicular to the first direction;
forming a corner spacer on the dummy dielectric layer at a corner formed by a sidewall of the dummy dielectric layer and a sidewall of the gate spacer; and
forming a gate structure over the fin and along a sidewall of the fin, the sidewall of the gate spacer, and a sidewall of the corner spacer.