US 12,294,021 B2
Semiconductor memory device
Tomonori Kajino, Yokkaichi (JP); Taichi Iwasaki, Yokkaichi (JP); Tatsuya Fujishima, Yokkaichi (JP); Masayuki Shishido, Yokkaichi (JP); and Nozomi Kido, Yokkaichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Mar. 7, 2024, as Appl. No. 18/598,073.
Application 18/598,073 is a continuation of application No. 17/470,982, filed on Sep. 9, 2021, granted, now 11,984,484.
Claims priority of application No. 2021-049130 (JP), filed on Mar. 23, 2021.
Prior Publication US 2024/0213339 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); G11C 16/04 (2006.01); H01L 29/423 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H01L 29/06 (2006.01)
CPC H01L 29/41775 (2013.01) [G11C 16/0483 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 29/0607 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a source line provided above the substrate;
a stacked structure portion provided in a same layer as the source line, the stacked structure portion including at least a first silicon layer;
a plurality of word lines provided above the source line, the word lines including tungsten and being spaced apart from each other in a first direction intersecting a surface of the substrate;
a pillar extending in the first direction and forming a memory cell at each of intersection portions with the word lines, a bottom portion of the pillar reaching the source line; and
a first member provided to extend in the first direction and provided with a first portion and a second portion in which the first portion is farther from the substrate than the second portion and a length of the first portion in the first direction is larger than a length of the second portion in the first direction, the first member including a first conductor and a first insulating film provided on a side surface portion of the first conductor,
the first conductor extending in the first direction from the first portion to the second portion of the first member, penetrating the stacked structure portion including the first silicon layer, being electrically connected to the substrate, and including a void correspondingly to the second portion of the first member.