	US 12,294,017 B2
	Semiconductor gate-all-around structure having carbon-doped anti-punch-through (APT) layers over wells
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,080.
Application 18/360,080 is a continuation of application No. 17/097,945, filed on Nov. 13, 2020, granted, now 11,784,226.
Prior Publication US 2023/0387212 A1, Nov. 30, 2023
Int. Cl. H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/1083 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/0638 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); H01L 27/092 (2013.01); H01L 29/66545 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

an n-type well and a p-type well over a substrate;

an n-type anti-punch-through (APT) layer over the n-type well;

a p-type APT layer over the p-type well;

an isolation feature disposed between the n-type APT layer and the p-type APT layer;

a first plurality of nanostructures disposed over the n-type APT layer;

a second plurality of nanostructures disposed over the p-type APT layer;

a first gate structure extending lengthwise along a first direction and wrapping around each of the first plurality of nanostructures; and

a second gate structure extending lengthwise along the first direction and wrapping around each of the second plurality of nanostructures,

wherein the n-type well is doped with phosphorus or arsenic,

wherein the p-type well is doped with boron,

wherein the n-type APT layer and the p-type APT layer are doped with carbon.

10. A semiconductor device, comprising:

an n-type well and a p-type well over a substrate;

an n-type anti-punch-through (APT) layer over the n-type well;

a p-type APT layer over the p-type well;

an isolation feature disposed between the n-type APT layer and the p-type APT layer;

a first plurality of nanostructures disposed over the n-type APT layer;

a second plurality of nanostructures disposed over the p-type APT layer;

a first gate structure extending lengthwise along a first direction and wrapping around each of the first plurality of nanostructures;

a second gate structure extending lengthwise along the first direction and wrapping around each of the second plurality of nanostructures;

two p-type source/drain features sandwiching the first plurality of nanostructures along a second direction perpendicular to the first direction; and

two n-type source/drain features sandwiching the second plurality of nanostructures along the second direction,

wherein the two p-type source/drain features extend below a top surface of the n-type APT layer by a first depth,

wherein the two n-type source/drain features extend below a top surface of the p-type APT layer by a second depth smaller than the first depth.

17. A semiconductor structure, comprising:

an n-type well and a p-type well over a substrate;

an n-type anti-punch-through (APT) layer over the n-type well;

a p-type APT layer over the p-type well;

an isolation feature disposed over the n-type well and the p-type well and disposed between the n-type APT layer and the p-type APT layer;

a first plurality of nanostructures disposed over the n-type APT layer;

a second plurality of nanostructures disposed over the p-type APT layer;

a first gate structure extending lengthwise along a first direction and wrapping around each of the first plurality of nanostructures; and

a second gate structure extending lengthwise along the first direction and wrapping around each of the second plurality of nanostructures,

wherein the n-type well is doped with phosphorus or arsenic,

wherein the p-type well is doped with boron,

wherein the n-type APT layer and the p-type APT layer are doped with carbon,

wherein the first gate structure and the second gate structure are sandwiched between a first gate end dielectric feature and a second gate end dielectric feature along the first direction.