US 12,294,008 B2
Semiconductor device and display device
Hajime Kimura, Kanagawa (JP); and Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on May 20, 2020, as Appl. No. 16/878,755.
Application 16/878,755 is a continuation of application No. 16/275,385, filed on Feb. 14, 2019, granted, now 10,665,612.
Application 16/275,385 is a continuation of application No. 15/810,228, filed on Nov. 13, 2017, granted, now 10,269,833, issued on Apr. 23, 2019.
Application 15/810,228 is a continuation of application No. 15/334,397, filed on Oct. 26, 2016, granted, now 9,825,059, issued on Nov. 21, 2017.
Application 15/334,397 is a continuation of application No. 15/231,851, filed on Aug. 9, 2016, granted, now 9,847,352, issued on Dec. 19, 2017.
Application 15/231,851 is a continuation of application No. 14/658,403, filed on Mar. 16, 2015, granted, now 9,418,989, issued on Aug. 16, 2016.
Application 14/658,403 is a continuation of application No. 12/875,808, filed on Sep. 3, 2010, granted, now 9,236,377, issued on Jan. 12, 2016.
Claims priority of application No. 2009-209099 (JP), filed on Sep. 10, 2009.
Prior Publication US 2021/0028194 A1, Jan. 28, 2021
Int. Cl. H01L 27/12 (2006.01); G02F 1/133 (2006.01); G02F 1/1339 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G11C 19/28 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G09G 3/36 (2006.01)
CPC H01L 27/1225 (2013.01) [G02F 1/13306 (2013.01); G02F 1/1339 (2013.01); G02F 1/136213 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G11C 19/28 (2013.01); H01L 27/088 (2013.01); H01L 27/124 (2013.01); H01L 27/1244 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G02F 1/133302 (2021.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A display device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a fifth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,
wherein a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the fourth wiring is configured such that a signal is input to the fourth wiring from the third wiring through the third transistor, and
wherein the fourth wiring is configured such that an electrical continuity from the first wiring is not established.