US 12,294,005 B2
Semiconductor device having a plurality of channel layers and method of manufacturing the same
Woo Cheol Shin, Suwon-si (KR); Myung Gil Kang, Suwon-si (KR); Sadaaki Masuoka, Suwon-si (KR); Sang Hoon Lee, Suwon-si (KR); and Sung Man Whang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/521,253.
Application 17/030,841 is a division of application No. 16/439,999, filed on Jun. 13, 2019, granted, now 10,833,085.
Application 18/521,253 is a continuation of application No. 17/894,427, filed on Aug. 24, 2022, granted, now 11,862,639.
Application 17/894,427 is a continuation of application No. 17/030,841, filed on Sep. 24, 2020, granted, now 11,437,377.
Claims priority of application No. 10-2019-0000559 (KR), filed on Jan. 3, 2019.
Prior Publication US 2024/0096894 A1, Mar. 21, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01)] 17 Claims
OG exemplary drawing
 
10. A semiconductor device, comprising:
a first semiconductor layer including a first region and a second region;
a buried insulating layer on the first semiconductor layer in the first region;
a second semiconductor layer on the buried insulating layer;
a base layer on the first semiconductor layer in the second region;
a plurality of first channel layers spaced apart from each other in a vertical direction on the first semiconductor layer in the first region;
a first gate electrode surrounding the plurality of first channel layers;
a plurality of second channel layers spaced apart from one another in the vertical direction on the base layer in the second region; and
a second gate electrode surrounding the plurality of second channel layers,
wherein the first semiconductor layer has a first crystallographic orientation, and the second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation,
wherein the plurality of second channel layers include a first channel component layer, a second channel component layer, and a third channel component layer formed in that sequence on the first semiconductor layer in the second region,
wherein a thickness of the third channel component layer is greater than a thickness of the second channel component layer, and
the thickness of the second channel component layer is greater than a thickness of the first channel component layer.