CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01)] | 17 Claims |
10. A semiconductor device, comprising:
a first semiconductor layer including a first region and a second region;
a buried insulating layer on the first semiconductor layer in the first region;
a second semiconductor layer on the buried insulating layer;
a base layer on the first semiconductor layer in the second region;
a plurality of first channel layers spaced apart from each other in a vertical direction on the first semiconductor layer in the first region;
a first gate electrode surrounding the plurality of first channel layers;
a plurality of second channel layers spaced apart from one another in the vertical direction on the base layer in the second region; and
a second gate electrode surrounding the plurality of second channel layers,
wherein the first semiconductor layer has a first crystallographic orientation, and the second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation,
wherein the plurality of second channel layers include a first channel component layer, a second channel component layer, and a third channel component layer formed in that sequence on the first semiconductor layer in the second region,
wherein a thickness of the third channel component layer is greater than a thickness of the second channel component layer, and
the thickness of the second channel component layer is greater than a thickness of the first channel component layer.
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