US 12,294,002 B2
Integrated circuit package and method of forming same
Shang-Yun Hou, Jubei (TW); Sung-Hui Huang, Dongshan Township (TW); Kuan-Yu Huang, Taipei (TW); Hsien-Pin Hu, Zhubei (TW); Yushun Lin, Taipei (TW); Heh-Chang Huang, Hsinchu (TW); Hsing-Kuo Hsia, Jhubei (TW); Chih-Chieh Hung, Hsinchu (TW); Ying-Ching Shih, Hsinchu (TW); Chin-Fu Kao, Taipei (TW); Wen-Hsin Wei, Hsinchu (TW); Li-Chung Kuo, Taipei (TW); Chi-Hsi Wu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 15, 2024, as Appl. No. 18/664,483.
Application 18/664,483 is a division of application No. 17/355,433, filed on Jun. 23, 2021, granted, now 12,015,023.
Application 17/355,433 is a division of application No. 16/051,848, filed on Aug. 1, 2018, granted, now 11,101,260, issued on Aug. 24, 2021.
Claims priority of provisional application 62/625,062, filed on Feb. 1, 2018.
Prior Publication US 2024/0297166 A1, Sep. 5, 2024
Int. Cl. H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 23/24 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/50 (2013.01) [H01L 21/4803 (2013.01); H01L 21/4853 (2013.01); H01L 23/24 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1144 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
a substrate;
a first integrated circuit die bonded to a first side of the substrate;
a second integrated circuit die bonded to the first side of the substrate adjacent the first integrated circuit die;
an annular structure bonded to a topmost surface of the first integrated circuit die;
an encapsulant over the substrate and surrounding the annular structure, the first integrated circuit die and the second integrated circuit die, wherein a topmost surface of the encapsulant is level with a topmost surface of the annular structure and a topmost surface of the second integrated circuit die; and
a functional component within the annular structure and bonded to the topmost surface of the first integrated circuit die.