US 12,293,999 B2
3D semiconductor package including memory array
Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Han-Jong Chia, Hsinchu (TW); Sheng-Chen Wang, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/814,194.
Application 17/814,194 is a continuation of application No. 17/138,270, filed on Dec. 30, 2020, granted, now 11,444,069.
Claims priority of provisional application 63/045,279, filed on Jun. 29, 2020.
Prior Publication US 2022/0359486 A1, Nov. 10, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 29/24 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 29/24 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1441 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory array comprising:
a gate dielectric layer contacting a first word line; and
an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the gate dielectric layer is between the OS layer and the first word line, wherein a horizontal line intersects the first word line, the source line, and the bit line;
an interconnect structure on the memory array; and
an integrated circuit die bonded to the interconnect structure opposite the memory array, wherein the integrated circuit die is bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.