US 12,293,994 B2
Semiconductor device integration with an amorphous region
Vvss Satyasuresh Choppalli, Bangalore (IN); Anupam Dutta, Bangalore (IN); Rajendran Krishnasamy, Essex Junction, VT (US); Robert Gauthier, Jr., Williston, VT (US); Xiang Xiang Lu, Essex Junction, VT (US); and Anindya Nath, Essex Junction, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Sep. 28, 2022, as Appl. No. 17/955,225.
Prior Publication US 2024/0105683 A1, Mar. 28, 2024
Int. Cl. H01L 25/07 (2006.01); H01L 21/77 (2017.01); H01L 23/14 (2006.01); H01L 23/522 (2006.01)
CPC H01L 25/072 (2013.01) [H01L 21/77 (2013.01); H01L 23/147 (2013.01); H01L 23/5228 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a semiconductor substrate;
a first device structure including a first well and a second well in the semiconductor substrate, the first well having a first conductivity type, the second well having a second conductivity type opposite to the first conductivity type, and the first well adjoining the second well to define a first p-n junction;
a second device structure including a doped region in the semiconductor substrate, the doped region has the first conductivity type or the second conductivity type; and
a first high-resistivity region in the semiconductor substrate, the first high-resistivity region having a higher electrical resistivity than the semiconductor substrate, and the first high-resistivity region positioned between the first device structure and the second device structure,
wherein the first device structure and the second device structure are different device structure types, the first device structure is a bipolar junction transistor, and the second device structure is a field-effect transistor.