US 12,293,993 B2
3D chip sharing data bus
Javier A. DeLaCruz, San Jose, CA (US); Steven L. Teig, Menlo Park, CA (US); and Ilyas Mohammed, San Jose, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Inc., San Jose, CA (US)
Filed on Oct. 13, 2023, as Appl. No. 18/379,925.
Application 18/379,925 is a continuation of application No. 17/105,272, filed on Nov. 25, 2020, granted, now 11,824,042.
Application 17/105,272 is a continuation of application No. 16/806,854, filed on Mar. 2, 2020, granted, now 10,892,252, issued on Jan. 12, 2021.
Application 16/806,854 is a continuation of application No. 15/976,811, filed on May 10, 2018, granted, now 10,580,757, issued on Mar. 3, 2020.
Application 15/976,811 is a continuation in part of application No. 15/725,030, filed on Oct. 4, 2017, granted, now 10,522,352, issued on Dec. 31, 2019.
Claims priority of provisional application 62/619,910, filed on Jan. 21, 2018.
Claims priority of provisional application 62/575,240, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,184, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,259, filed on Oct. 20, 2017.
Claims priority of provisional application 62/405,833, filed on Oct. 7, 2016.
Prior Publication US 2024/0266325 A1, Aug. 8, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 21/822 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/60 (2006.01); H01L 25/00 (2006.01); H01L 27/06 (2006.01); H01L 23/50 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/8221 (2013.01); H01L 23/49827 (2013.01); H01L 23/5225 (2013.01); H01L 23/528 (2013.01); H01L 23/5286 (2013.01); H01L 23/60 (2013.01); H01L 24/32 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 23/50 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/09181 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device package comprising:
a first device comprising first metal line layers;
a second device comprising second metal line layers; and
one or more direct bonded interconnects coupling the first metal line layers to the second metal line layers, the one or more direct bonded interconnects defining an unserialized data path.