US 12,293,992 B2
Semiconductor assemblies with systems and methods for managing high die stack structures
Kelvin Tan Aik Boo, Singapore (SG); Seng Kim Ye, Singapore (SG); Chin Hui Chong, Singapore (SG); and Hong Wan Ng, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 24, 2023, as Appl. No. 18/225,369.
Application 18/225,369 is a continuation of application No. 17/233,129, filed on Apr. 16, 2021, granted, now 11,710,722.
Prior Publication US 2023/0369291 A1, Nov. 16, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/4985 (2013.01); H01L 24/48 (2013.01); H01L 25/50 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06572 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a rigid flex circuit having a first rigid region and a second rigid region electrically connected by a flexible portion, wherein the first and second rigid regions include a soldermask material absent from the flexible portion;
a first die mounted to a first surface of the first rigid region; and
a second die mounted to a second surface of the second rigid region, the first and second surfaces being on a same side of the rigid flex circuit, wherein the flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.