US 12,293,990 B2
Semiconductor integrated circuit comprising master chip with first buffer circuit and slave chiip with second buffer circuit
Yun Gi Hong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 22, 2022, as Appl. No. 17/700,965.
Claims priority of application No. 10-2021-0130334 (KR), filed on Sep. 30, 2021.
Prior Publication US 2023/0112669 A1, Apr. 13, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/48 (2006.01); H03K 3/3562 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H03K 3/35625 (2013.01); H01L 2225/06513 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a master chip including a first buffer circuit coupled to a first power line that is supplied with a first voltage and a first supply circuit that supplies a second voltage, having a lower voltage level than the first voltage, to a first through line in response to a control signal; and
a slave chip, coupled to the first through line, including a second buffer circuit coupled to a second power line supplied with the second voltage and a second supply circuit that supplies the second voltage to a second through line in response to the control signal, which indicates whether the master chip and the slave chip are stacked.