US 12,293,989 B2
Semiconductor package
Minjung Kim, Cheonan-si (KR); Dongkyu Kim, Anyang-si (KR); Jongyoun Kim, Seoul (KR); and Seokhyun Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 25, 2022, as Appl. No. 17/680,857.
Claims priority of application No. 10-2021-0111542 (KR), filed on Aug. 24, 2021.
Prior Publication US 2023/0065378 A1, Mar. 2, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/105 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first redistribution substrate;
a lower semiconductor chip on the first redistribution substrate, the lower semiconductor chip including a through via therein;
a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip;
an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure, the upper semiconductor chip being coupled to the through via and the second lower conductive structure;
an upper conductive structure on the first lower conductive structure; and
an upper molding layer covering a sidewall of the upper semiconductor chip and a sidewall of the upper conductive structure,
wherein a width of the second lower conductive structure is greater than a width of the through via, and
wherein the upper conductive structure comprises an upper post laterally spaced apart from the upper semiconductor chip.