US 12,293,985 B2
Integrated circuit packages and methods of forming the same
Chih-Chia Hu, Taipei (TW); Ming-Fa Chen, Taichung (TW); and Sung-Feng Yeh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/870,816.
Application 17/870,816 is a division of application No. 16/398,159, filed on Apr. 29, 2019, granted, now 11,562,982.
Prior Publication US 2022/0359462 A1, Nov. 10, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/6835 (2013.01); H01L 23/562 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2221/68354 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package, comprising:
an integrated circuit structure;
a first die stack, comprising a plurality of first die structures and bonded to the integrated circuit structure at a first side of the first die stack, wherein the first die stack is directly in contact with the integrated circuit structure; and
a dummy die, comprising a plurality of through substrate vias, located aside the first die stack and electrically connected to the integrated circuit structure at the first side of the first die stack, wherein a height of the through substrate vias of the dummy die is the same as a height of the first die stack, a gap between the first die stack and the dummy die is filled with air, and the first die stack is laterally surrounded by the air, and wherein the dummy die further includes two insulating layers respectively surrounding top and bottom portions of the through substrate via, and the two insulating layers are directly in contact with the air.