US 12,293,981 B2
Electronic circuit comprising a RF switches having reduced parasitic capacitances
Stephane Monfray, Eybens (FR); Siddhartha Dhar, Grenoble (FR); and Alain Fleury, Barberaz (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 29, 2022, as Appl. No. 17/733,589.
Claims priority of application No. 2104781 (FR), filed on May 6, 2021.
Prior Publication US 2022/0359435 A1, Nov. 10, 2022
Int. Cl. H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/373 (2006.01); H01L 23/42 (2006.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01)
CPC H01L 23/66 (2013.01) [H01L 21/4882 (2013.01); H01L 23/3736 (2013.01); H01L 23/42 (2013.01); G11C 13/0004 (2013.01); H01L 2223/6677 (2013.01); H10N 70/8413 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a semiconductor substrate;
MOS (metal oxide semiconductor) transistors on the semiconductor substrate;
radiofrequency switches corresponding to the MOS transistors, the radiofrequency switches comprising:
doped semiconductor regions in the semiconductor substrate;
at least two metallization levels on the semiconductor substrate, each metallization level comprising:
a stack of insulating layers including an upper insulating layer with an upper surface facing away from the semiconductor substrate;
a conductive pillar extending through the stack of insulating layers;
a metallic track within the stacked insulating layers and coupled to the conductive pillars; and
at least two connection elements each connecting one of the doped semiconductor regions including ones of the conductive pillars and ones of the metallic tracks of the at least two metallization levels;
a trench between the two connection elements, the trench overlaps a first one of the MOS transistors on the semiconductor substrate, the trench is delimited by respective sidewalls of the stack of insulating layers and is delimited by a respective end surface of a respective insulating layer of the stack of insulating layers; and
a heat dissipation structure within the trench, the heat dissipation structure overlaps the first one of the MOS transistors, and the heat dissipation structure is configured to dissipate heat out of the trench, the heat dissipation structure including:
a heat dissipation coating extends along the respective end surface, extends along the respective sidewalls, and extends along the upper surface of the upper insulating layer; and
a plug in the trench and on the heat dissipation coating, the plug and the heat dissipation coating entirely filling the trench.