CPC H01L 23/552 (2013.01) [H01L 21/4817 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 23/053 (2013.01); H01L 23/3128 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/48157 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/3025 (2013.01)] | 20 Claims |
1. A semiconductor package comprising:
a package substrate;
at least one semiconductor chip on an upper surface of the package substrate;
a conductive wall that extends around sides of the at least one semiconductor chip above the package substrate;
a molded body covering the at least one semiconductor chip and at least a portion of the upper surface of the package substrate;
a shielding cover that covers the molded body and the conductive wall; and
an adhesive between the conductive wall and the package substrate,
wherein the package substrate comprises a base, a solder resist layer on an upper surface of the base, and a protrusion contacting the base and extending into the solder resist layer, and
the protrusion is electrically connected to the conductive wall.
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