US 12,293,976 B2
Semiconductor EMI shielding component, semiconductor package structure and manufacturing method thereof
E-Tung Chou, Hsinchu County (TW); and Po-Han Chiu, Hsinchu County (TW)
Assigned to Phoenix Pioneer Technology Co., Ltd., Hsinchu County (TW)
Filed by Phoenix Pioneer Technology Co., Ltd., Hsinchu County (TW)
Filed on Jul. 6, 2022, as Appl. No. 17/858,286.
Claims priority of application No. 110130084 (TW), filed on Aug. 16, 2021.
Prior Publication US 2023/0048468 A1, Feb. 16, 2023
Int. Cl. H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01); H01L 23/00 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 23/49838 (2013.01); H01L 25/165 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/182 (2013.01); H01L 2924/3025 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a package carrier, which has a first surface, a second surface, a build-up circuit, and a first dielectric layer, wherein, the first surface and the second surface are disposed oppositely and the first dielectric layer covers the build-up circuit;
at least one electronic component, which is disposed on the first surface of the package carrier and is electrically connected to the build-up circuit;
a packaging layer, which is disposed on the first surface of the package carrier and covers the electronic component;
a support component, which is embedded in the packaging layer and at least surrounds the electronic component, one end surface of the support component is exposed to a surface of the packaging layer, and the other end surface of the support component is electrically connected to the build-up circuit of the package carrier and electrically grounded; and
a shielding layer, which is disposed on the packaging layer and the support component and has a patterned metal layer and a second dielectric layer, wherein, the second dielectric layer covers the patterned metal layer, the patterned metal layer is electrically connected to the support component, and the shielding range of the patterned metal layer covers at least the electronic component and the support component;
wherein, the support component and the shielding layer together form a shielding space to surround the electronic component.