US 12,293,970 B2
Semiconductor structure and method for manufacturing thereof
Shih-Hsiang Kao, Hsinchu (TW); and Chi-Wen Chang, Changhua County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,668.
Prior Publication US 2023/0065397 A1, Mar. 2, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/76802 (2013.01); H01L 23/50 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate; and
a metallization layer over the substrate, the metallization layer comprises a plurality of first rows and a plurality of second rows alternately arranged between a power rail and a ground rail parallel to the power rail, the first rows are parallel to the second rows, the metallization layer further comprises:
a plurality of signal lines arranged in the first row and the second row, the plurality of signal lines in the first row comprises:
a first signal line, a second signal line, and a third signal line, the first signal line, the
second signal line, and the third signal line are parallel to the power rail; and
a plurality of vias in contact with the plurality of signal lines in the first row and the second row, each of the signal lines in the first rows is free from having a dummy portion, at least a signal line in each of the second rows comprises a dummy portion;
wherein a first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line.