US 12,293,969 B2
Semiconductor structure and manufacturing method thereof
Chi-Ta Lu, Yilan County (TW); and Chi-Ming Tsai, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/816,277.
Application 17/816,277 is a continuation of application No. 17/026,283, filed on Sep. 20, 2020, granted, now 11,476,193.
Application 17/026,283 is a continuation of application No. 16/212,112, filed on Dec. 6, 2018, granted, now 10,784,196, issued on Sep. 22, 2020.
Claims priority of provisional application 62/736,967, filed on Sep. 26, 2018.
Prior Publication US 2022/0367356 A1, Nov. 17, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76879 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a dielectric layer disposed over the substrate;
a conductive line surrounded by the dielectric layer and extending over the substrate; and
a conductive via disposed over the conductive line and extending through the dielectric layer,
wherein a first interface between the conductive via and the dielectric layer is substantially coplanar with a second interface between the conductive via and the conductive line.