US 12,293,959 B2
Through-circuit Vias in interconnect structures
Jian-Hong Lin, Yunlin (TW); Hsin-Chun Chang, Taipei (TW); Ming-Hong Hsieh, Bade (TW); Ming-Yih Wang, Hsin-Chu (TW); and Yinlung Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/232,200.
Application 18/232,200 is a division of application No. 17/815,997, filed on Jul. 29, 2022.
Application 17/815,997 is a division of application No. 17/162,584, filed on Jan. 29, 2021, granted, now 11,616,002, issued on Mar. 28, 2023.
Claims priority of provisional application 63/029,863, filed on May 26, 2020.
Prior Publication US 2023/0386973 A1, Nov. 30, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76843 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a semiconductor device on a front surface of a substrate;
forming a first interconnect structure on the front surface of the substrate;
performing a thin down process on a back surface of the substrate;
forming a first portion of a second interconnect structure on a back surface of the thinned down substrate;
forming a through-via opening extending through the first portion of the second interconnect structure, the substrate, and the first interconnect structure;
depositing a conductive liner along sidewalls of the through-via opening;
depositing a conductive plug on the conductive liner; and
forming a second portion of the second interconnect structure on the conductive plug.