| CPC H01L 23/481 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01)] | 18 Claims |
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1. A semiconductor device comprising:
a substrate which comprises a first surface and a second surface opposing each other;
a hard macro which is disposed on the first surface of the substrate and comprises a cell area and a halo area formed along a periphery of the cell area, and a first connection wiring disposed at a first metal level, the first connection wiring including a first wire, the first wire comprising a single linear segment that extends continuously from the cell area to the halo area at the first metal level;
a first power rail which is disposed on the second surface of the substrate and receives a first voltage; and
a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring,
wherein the first through via is a single structure, and
wherein a portion of a bottom surface of the first wire directly contacts an upper surface of the first through via.
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