US 12,293,957 B2
Optimization of the thermal performance of the 3D ICs utilizing the integrated chip-size double-layer or multi-layer microchannels
Kambiz Vafai, Mission Viejo, CA (US); and Sainan Lu, Jurupa Valley, CA (US)
Assigned to Kambix Innovations II, LLC, Albuquerque, NM (US)
Filed by Kambix Innovations, LLC, Albuquerque, NM (US)
Filed on Aug. 2, 2024, as Appl. No. 18/793,277.
Application 18/793,277 is a continuation of application No. 18/214,141, filed on Jun. 26, 2023, granted, now 12,087,663.
Claims priority of provisional application 63/356,873, filed on Jun. 29, 2022.
Prior Publication US 2025/0087556 A1, Mar. 13, 2025
Int. Cl. H01L 23/467 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/467 (2013.01) [H01L 25/0657 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of fabricating a three-dimensional (3D) integrated circuit (IC) apparatus, comprising:
forming a 3D IC structure comprising a substrate;
forming a plurality of integrated double-layer microchannels including a first set of integrated double-layer microchannels and a second set of integrated double-layer microchannels, wherein the 3D IC structure includes the plurality of integrated double-layer microchannels and
configuring the plurality of integrated double-layer microchannels in a structural arrangement to optimize a thermal performance for the 3D IC structure, wherein the first set of integrated double-layer microchannels is located immediately below a top of the 3D IC structure and the second set of integrated double-layer microchannels is located immediately above the substrate with the substrate located immediately above a bottom of the 3D IC structure.