US 12,293,956 B2
Boiling enhancement structures for immersion cooled electronic systems
Jin Yang, Hillsboro, OR (US); Jimmy Chuang, Taipei (TW); Xicai Jing, Shanghai (CN); Yuan-Liang Li, Taipei (TW); Yuyang Xia, Shanghai (CN); David Shia, Portland, OR (US); Mohanraj Prabhugoud, Hillsboro, OR (US); Maria de la Luz Belmont, Zapopan (MX); Oscar Farias Moguel, Morelia (MX); Andres Ramirez Macias, Zapopan (MX); Javier Avalos Garcia, Zapopan (MX); Jessica Gullbrand, Hillsboro, OR (US); Shaorong Zhou, Shanghai (CN); Chia-Pin Chiu, Tempe, AZ (US); and Xiaojin Gu, Shanghai Zizhu Science Park (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/356,014.
Claims priority of provisional application 63/059,900, filed on Jul. 31, 2020.
Prior Publication US 2021/0327787 A1, Oct. 21, 2021
Int. Cl. H01L 23/44 (2006.01)
CPC H01L 23/44 (2013.01) 24 Claims
OG exemplary drawing
 
1. A system comprising:
a packaged semiconductor device;
an integrated heat spreader, thermally coupled to the packaged semiconductor device;
a first boiling enhancement layer located on a first side of the integrated heat spreader; and
a second boiling enhancement layer located on a second side of the integrated heat spreader, the second side opposite the first side, each of the first boiling enhancement layer and the second boiling enhancement layer having a non-planar surface.