US 12,293,955 B2
High power module package structures
Yusheng Lin, Phoenix, AZ (US); and Jerome Teysseyre, Singapore (SG)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Nov. 6, 2023, as Appl. No. 18/502,162.
Application 17/443,307 is a division of application No. 16/243,505, filed on Jan. 9, 2019, granted, now 11,075,137, issued on Jul. 27, 2021.
Application 18/502,162 is a continuation of application No. 17/443,307, filed on Jul. 23, 2021, granted, now 11,810,775.
Application 16/243,505 is a continuation in part of application No. 16/145,918, filed on Sep. 28, 2018, granted, now 10,991,670, issued on Apr. 27, 2021.
Claims priority of provisional application 62/665,598, filed on May 2, 2018.
Prior Publication US 2024/0071860 A1, Feb. 29, 2024
Int. Cl. H01L 23/373 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 23/051 (2006.01); H01L 23/31 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01)
CPC H01L 23/3735 (2013.01) [H01L 21/52 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/4334 (2013.01); H01L 23/49822 (2013.01); H01L 24/20 (2013.01); H01L 25/0657 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01); H01L 29/7393 (2013.01); H01L 29/861 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier, the semiconductor die being thermally coupled to the first high voltage isolation carrier via a first coupling mechanism and a second coupling mechanism;
a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and between the first coupling mechanism and the second coupling mechanism; and
a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier, the conductive spacer thermally coupled to the semiconductor die and to the second high voltage isolation carrier, wherein a lateral dimension of the conductive spacer is greater than a lateral dimension of the semiconductor die,
the molding material encapsulating the semiconductor die and the conductive spacer.