US 12,293,946 B2
Techniques for wafer stack processing
Yung-Lung Lin, Taichung (TW); Cheng-Hsien Chou, Tainan (TW); Cheng-Yuan Tsai, Chu-Pei (TW); Kuo-Ming Wu, Zhubei (TW); and Hau-Yi Hsiao, Chiayi (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 7, 2022, as Appl. No. 18/076,701.
Application 17/406,249 is a division of application No. 16/866,685, filed on May 5, 2020, granted, now 11,127,635, issued on Sep. 21, 2021.
Application 18/076,701 is a continuation of application No. 17/406,249, filed on Aug. 19, 2021, granted, now 11,545,395.
Prior Publication US 2023/0101989 A1, Mar. 30, 2023
Int. Cl. H01L 21/822 (2006.01); H01L 21/304 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 21/304 (2013.01); H01L 27/0688 (2013.01); H01L 29/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a first substrate comprising a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view, wherein the first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view;
a second substrate disposed over the first substrate and comprising a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view, wherein the second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view;
wherein the first horizontally extending surface is a flat surface that is entirely laterally outside of the second substrate; and
wherein the second horizontally extending surface is a flat surface that is entirely laterally outside of the second substrate and that is vertically between an overlying sidewall of the first substrate and an underlying sidewall of the first substrate.