US 12,293,944 B2
Semiconductor device with self-aligned vias
Chien-Han Chen, Nantou (TW); Chien-Chih Chiu, Xinying (TW); and Ming-Chung Liang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/750,887.
Application 17/750,887 is a continuation of application No. 16/275,109, filed on Feb. 13, 2019, granted, now 11,502,001.
Claims priority of provisional application 62/753,496, filed on Oct. 31, 2018.
Prior Publication US 2022/0285216 A1, Sep. 8, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/76807 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76865 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 21/02211 (2013.01); H01L 21/31122 (2013.01); H01L 21/32134 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming a conductive line in the first dielectric layer, wherein forming the conductive line comprises:
forming a first dielectric film and a second dielectric film successively over the first dielectric layer;
forming a recess in the second dielectric film using a first etching process, wherein after the first etching process, an upper surface of the first dielectric film distal from the substrate is exposed at a bottom of the recess;
after the first etching process, extending the recess through the first dielectric film and the first dielectric layer using a second etching process different from the first etching process;
after extending the recess, filling the recess with a first electrically conductive material, wherein the first electrically conductive material extends along sidewalls of the first dielectric layer, sidewalls of the first dielectric film, and sidewalls of the second dielectric film; and
after filling the recess, performing a planarization process to remove the first dielectric film, the second dielectric film, and portions of the first electrically conductive material embedded in the first dielectric film and the second dielectric film, wherein remaining portions of the first electrically conductive material embedded in the first dielectric layer form the conductive line;
forming an etch stop layer (ESL) over the conductive line and over an upper surface of the first dielectric layer distal from the substrate, wherein a first lower surface of the ESL contacting an upper surface of the conductive line is closer to the substrate than a second lower surface of the ESL over the upper surface of the first dielectric layer;
forming a second dielectric layer over the ESL;
forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL disposed on the conductive line, exposing a second portion of the ESL disposed along a first sidewall of the first dielectric layer, and exposing a third portion of the ESL disposed on the upper surface of the first dielectric layer, wherein the second portion of the ESL connects the first portion and the third portion of the ESL;
removing the first portion of the ESL to expose the conductive line and removing the second portion and the third portion of the ESL to expose the first sidewall and the upper surface of the first dielectric layer; and
filling the opening with a second electrically conductive material to form a via.