US 12,293,925 B2
Semiconductor device and method of manufacturing the same
Yuki Murayama, Tokyo (JP); Makoto Koshimizu, Tokyo (JP); Takahiro Mori, Tokyo (JP); Junjiro Sakai, Tokyo (JP); and Satoshi Iida, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Aug. 24, 2022, as Appl. No. 17/894,579.
Claims priority of application No. 2021-144539 (JP), filed on Sep. 6, 2021.
Prior Publication US 2023/0069864 A1, Mar. 9, 2023
Int. Cl. H01L 21/4757 (2006.01); H01L 21/311 (2006.01); H01L 21/475 (2006.01); H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/47573 (2013.01) [H01L 21/31144 (2013.01); H01L 21/475 (2013.01); H01L 21/47635 (2013.01); H01L 23/3171 (2013.01); H01L 23/522 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 24/05 (2013.01); H01L 21/76837 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
(a) sequentially forming a plurality of elements and an interlayer insulating film on a substrate;
(b) forming a plurality of first wirings, a second wiring, a plurality of first dummy wirings, and a second dummy wiring on the interlayer insulating film;
(c) forming an insulating film that covers each of an upper surface of the interlayer insulating film, the plurality of first wirings, the second wiring, the plurality of first dummy wirings, and the second dummy wiring;
(d) coating a photoresist film on the insulating film by spin coating;
(e) forming a resist pattern formed by the photoresist film; and
(f) performing etching with the resist pattern used as a mask to remove part of the insulating film, and exposing an upper surface of part of the plurality of first wirings,
wherein the plurality of first wirings are disposed to surround the second wiring in plan view,
wherein the plurality of first dummy wirings are disposed in a vicinity of each of the plurality of first wirings,
wherein some of the plurality of elements constitute an analog circuit portion,
wherein the second wiring and the second dummy wiring are disposed at such a position as to overlap with the analog circuit portion in plan view,
wherein the second dummy wiring is disposed around the second wiring in a vicinity of the second wiring,
wherein a shortest distance between the second dummy wiring and the plurality of first wirings is larger than a shortest distance between adjacent ones of the first wirings, and
wherein, in the (c), regarding a film thickness of the insulating film formed directly above each of the plurality of first wirings, the second wiring, the plurality of first dummy wirings, and the second dummy wiring, a film thickness of the insulating film formed directly above a center portion of each of the plurality of first wirings, the second wiring, the plurality of first dummy wirings, and the second dummy wiring is larger than a film thickness of the insulating film formed directly above both end portions of each of the plurality of first wirings, the second wiring, the plurality of first dummy wirings, and the second dummy wiring.