US 12,293,919 B2
Alternating etch and passivation process
Seongjun Heo, Dublin, CA (US); Jengyi Yu, San Ramon, CA (US); Chen-Wei Liang, El Cerrito, CA (US); Alan J. Jensen, Mountain House, CA (US); and Samantha S. H. Tan, Newark, CA (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Filed by Lam Research Corporation, Fremont, CA (US)
Filed on Nov. 8, 2023, as Appl. No. 18/505,043.
Application 18/505,043 is a continuation of application No. 18/056,468, filed on Nov. 17, 2022, granted, now 11,848,212.
Application 18/056,468 is a continuation of application No. 17/596,921, granted, now 11,551,938, issued on Jan. 10, 2023, previously published as PCT/US2020/038996, filed on Jun. 22, 2020.
Claims priority of provisional application 62/867,797, filed on Jun. 27, 2019.
Prior Publication US 2024/0087904 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/67 (2006.01)
CPC H01L 21/30655 (2013.01) [H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/67069 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of processing a semiconductor substrate, the method comprising:
(a) providing a semiconductor substrate having an exposed silicon-containing material and an exposed tin oxide,
wherein the exposed silicon-containing material comprises carbon;
(b) passivating the exposed silicon-containing material towards a tin oxide etch chemistry;
(c) etching the exposed tin oxide using the tin oxide etch chemistry; and
(d) repeating operations (b) and (c) such that operations (b) and (c) are performed in an alternating fashion.