| CPC H01L 21/3065 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 27/0727 (2013.01)] | 20 Claims |
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1. A method, comprising:
providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region;
forming a first well region of a second conductivity type in the first circuit region of the substrate;
forming a first doped region of the second conductivity type in the first well region;
forming a diode in the second circuit region of the substrate;
forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively;
forming a discharge structure over the substrate to electrically couple the first doped region to the diode, wherein the discharge structure directly contacts the diode; and
forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein
the forming of at least one of the first doped region, the diode, the first transistor, the second transistor, the discharge structure and metallization layer includes a plasma-enhanced operation, which causes negative charges to accumulate in the first well region, and wherein the negative charges are drained from the first well region to the substrate through the first doped region, and the discharge structure and the diode, wherein
the first well region is an N-well region,
the diode includes a P-N junction at an interface between the substrate and a second doped region of the second conductivity type in the substrate, and
the discharge structure directly contacts the first well region.
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