US 12,293,916 B2
Surface oxidation control of metal gates using capping layer
Pei-Yu Chou, Hsinchu (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/230,712.
Application 18/230,712 is a division of application No. 17/191,105, filed on Mar. 3, 2021, granted, now 12,046,475.
Claims priority of provisional application 63/137,201, filed on Jan. 14, 2021.
Prior Publication US 2023/0386848 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/28247 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 29/401 (2013.01); H01L 29/66454 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/31116 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a source/drain region extending into a semiconductor region;
forming a replacement gate stack on the semiconductor region;
forming a first inter-layer dielectric over the source/drain region, wherein a portion of the replacement gate stack is in the first inter-layer dielectric;
depositing a dielectric capping layer, wherein a bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric;
depositing a second inter-layer dielectric over the dielectric capping layer;
forming a source/drain contact plug extending into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric;
depositing an etch stop layer over the second inter-layer dielectric;
depositing a third inter-layer dielectric over the etch stop layer;
performing a first etching process to etch the third inter-layer dielectric and to form a first contact opening, wherein the first etching process is stopped on the etch stop layer;
performing a second etching process to etch the etch stop layer and to extend the first contact opening to the source/drain contact plug; and
performing a third etching process to etch the third inter-layer dielectric, the etch stop layer, the second inter-layer dielectric, and the dielectric capping layer in a continuous etching process to form a second contact opening and to expose the replacement gate stack.