US 12,293,914 B2
Semiconductor device structure and method for preparing the same
Cheng-Hsiang Fan, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/231,912.
Application 17/511,042 is a division of application No. 16/811,824, filed on Mar. 6, 2020, granted, now 11,315,786.
Application 18/231,912 is a continuation in part of application No. 17/511,042, filed on Oct. 26, 2021, granted, now 11,776,813.
Prior Publication US 2023/0386842 A1, Nov. 30, 2023
Int. Cl. H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/0337 (2013.01) [H01L 21/308 (2013.01); H01L 21/31144 (2013.01); H01L 21/76229 (2013.01); H01L 21/764 (2013.01); H01L 21/76816 (2013.01); H01L 21/7682 (2013.01); H01L 21/76885 (2013.01); H01L 2221/1036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a substrate;
a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion connected to the first portion and the second portion, wherein a height of the first portion and a height of the second portion are greater than a height of the third portion;
a second target structure disposed over the substrate, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion connected to the fourth portion and the fifth portion;
a first low-level conductive pattern and a second low-level conductive pattern, both positioned between the first target structure and the second target structure;
a first high-level conductive pattern and a second high-level conductive pattern, both positioned in the first target structure;
a first conductive pillar and a second conductive pillar, disposed over the substrate, wherein the first conductive pillar overlaps and is electrically connected to the first low-level conductive pattern, and the second conductive pillar overlaps and is electrically connected to the second low-level conductive pattern;
a first landing pad and a second landing pad, disposed on the first and second conductive pillars, respectively, wherein the first landing pad overlaps and is electrically connected to the first conductive pillar, the second landing pad overlaps and is electrically connected to the second conductive pillar, sidewalls of the first and second conductive pillars are recessed from sidewalls of the first and second landing pads, the first and second landing pads are made of a conductive material different from a conductive material used to form the first and second conductive pillars, and a resistivity of the first and second landing pads is less than a resistivity of the first and second conductive pillars; and
a dielectric layer, laterally surrounding the first and second conductive pillars and the first and second landing pads, wherein the dielectric layer has an air gap between the first and second conductive pillars.