US 12,293,913 B1
Directed self-assembly enabled subtractive metal patterning
Gurpreet Singh, Portland, OR (US); Richard E. Schenker, Portland, OR (US); Nityan Labros Nair, Portland, OR (US); Nafees A. Kabir, Portland, OR (US); Gauri Nabar, Hillsboro, OR (US); Eungnak Han, Portland, OR (US); Xuanxuan Chen, Hillsboro, OR (US); Tayseer Mahdi, Beaverton, OR (US); Brandon Jay Holybee, Portland, OR (US); Charles Henry Wallace, Portland, OR (US); Paul A. Nyhus, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); and Florian Gstrein, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,363.
Int. Cl. H01L 23/532 (2006.01); H01L 21/027 (2006.01)
CPC H01L 21/0271 (2013.01) [H01L 23/53209 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a grating in an active region, the grating comprising a first plurality of conductive lines separated by a plurality of insulating lines, wherein a first pair of adjacent conductive lines in the first plurality of conductive lines are arranged at a pitch, the pitch less than 30 nanometers, and the first plurality of conductive lines comprises:
a first subset of conductive lines comprising a first metal, and
a second subset of conductive lines comprising a second metal different from the first metal; and
an inactive region adjacent to the active region, the inactive region comprising a second plurality of conductive lines, wherein a first line of the first plurality of conductive lines is coupled to a second line of the second plurality of conductive lines, and the first line is offset from the second line by less than the pitch.