US 12,293,910 B2
Interconnect structure for semiconductor devices
Po-Chuan Wang, Taipei (TW); Guan-Xuan Chen, Taoyuan (TW); Chia-Yang Hung, Kaohsiung (TW); Sheng-Liang Pan, Hsinchu (TW); and Huan-Just Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,552.
Application 18/359,552 is a division of application No. 17/232,465, filed on Apr. 16, 2021.
Claims priority of provisional application 63/085,217, filed on Sep. 30, 2020.
Prior Publication US 2023/0386821 A1, Nov. 30, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/02063 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76814 (2013.01); H01L 21/76883 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first conductive feature in a first dielectric layer;
forming a second dielectric layer over the first dielectric layer;
forming an opening in the second dielectric layer to expose an upper surface of the first conductive feature, wherein forming the opening comprises performing an anisotropic plasma etching process;
after forming the opening, treating the first conductive feature with a plasma process different from the anisotropic plasma etching process; and
after the plasma process, cleaning the opening using deionized water, wherein the cleaning enlarges a bottom portion of the opening, wherein the cleaning recesses the upper surface of the first conductive feature, and forms an undercut under the second dielectric layer, wherein the undercut extends beyond a sidewall of the second dielectric layer exposed by the opening.