CPC G11C 7/22 (2013.01) [G06F 11/1076 (2013.01); G11C 7/10 (2013.01); G11C 2207/2254 (2013.01)] | 21 Claims |
1. An apparatus comprising:
a memory controller, wherein the memory controller is configured to communicate with a memory via a plurality of signal paths, and wherein the memory controller includes a calibration circuit, wherein the calibration circuit is configured to:
perform a first calibration that includes activating each of the plurality of signal paths to determine respective eye patterns for signal paths in the plurality of signal paths; and
perform a second calibration subsequent to the first calibration, wherein the second calibration comprises activating a first subset of the plurality of the signal paths to determine update respective eye patterns for signal paths in the first subset, and, for signal paths of a second subset different from the first subset, determine respective updated eye patterns based on information obtained during the first calibration, wherein the second calibration is performed without activating the signal paths of the second subset.
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