US 12,293,806 B2
Static random-access memory (SRAM) apparatus and method for reducing wire delay
Lava Kumar Pulluru, Bengaluru (IN); Gopi Sunanth Kumar Gogineni, Bengaluru (IN); Manish Chandra Joshi, Bengaluru (IN); and Pushp Khatter, Bengaluru (IN)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 31, 2022, as Appl. No. 18/051,142.
Claims priority of application No. 202241049601 (IN), filed on Aug. 30, 2022.
Prior Publication US 2024/0071438 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 7/12 (2013.01); G11C 7/22 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A Static Random-Access Memory (SRAM) apparatus for reducing wire delay, the apparatus comprising:
a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, each of the segments comprising a plurality of memory bit cells, the plurality of columns in each of the left memory array and the right memory array are divided into the plurality of segments using one or more edge cells; and
central driver circuitry between the left memory array and the right memory array, the central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments, wherein the one or more edge cells are not connected to any metal control lines of the plurality of metal control lines.