US 12,293,805 B2
Manufacturing method of forming a semiconductor memory device with improved structural stability and process defects
Nam Jae Lee, Cheongju-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 1, 2022, as Appl. No. 17/856,741.
Application 17/856,741 is a continuation of application No. 16/884,599, filed on May 27, 2020, granted, now 11,410,708.
Claims priority of application No. 10-2019-0161844 (KR), filed on Dec. 6, 2019.
Prior Publication US 2022/0335980 A1, Oct. 20, 2022
Int. Cl. G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC G11C 5/025 (2013.01) [G11C 5/06 (2013.01); H01L 23/5226 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, comprising:
forming a preliminary stepped structure comprising interlayer insulating layers and horizontal sacrificial layers that are alternately stacked;
forming a pad sacrificial layer on a sidewall of each of the horizontal sacrificial layers;
forming a first hole passing through the pad sacrificial layer and the preliminary stepped structure;
forming a spacer insulating layer on a sidewall of the first hole;
forming a first sacrificial pillar on the spacer insulating layer to fill the first hole;
removing the horizontal sacrificial layers;
forming conductive patterns in horizontal spaces where the horizontal sacrificial layers are removed;
removing the first sacrificial pillar to expose the spacer insulating layer;
removing a portion of the spacer insulating layer to expose the pad sacrificial layer;
removing the pad sacrificial layer; and
forming a contact pattern that fills an area from which the pad sacrificial layer is removed and the first hole.